55 research outputs found
A heuristic approach for multiple restricted multiplication
Published versio
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators
© Springer International Publishing Switzerland 2016.As the threat of fault susceptibility caused by mechanisms including variation and degradation increases, engineers must give growing consideration to error detection and correction. While the use of common fault tolerance strategies frequently causes the incursion of significant overheads in area, performance and/or power consumption, options exist that buck these trends. In particular, algorithm-based fault tolerance embodies a proven family of low-overhead error mitigation techniques able to be built upon to create self-verifying circuitry. In this paper, we present our research into the application of algorithm-based fault tolerance (ABFT) in FPGA-implemented accelerators at reduced levels of precision. This allows for the introduction of a previously unexplored tradeoff: sacrificing the observability of faults associated with low-magnitude errors for gains in area, performance and efficiency by reducing the bit-widths of logic used for error detection. We describe the implementation of a novel checksum truncation technique, analysing its effects upon overheads and allowed error. Our findings include that bit-width reduction of ABFT circuitry within a fault-tolerant accelerator used for multiplying pairs of 32 × 32 matrices resulted in the reduction of incurred area overhead by 16.7% and recovery of 8.27% of timing model fmax. These came at the cost of introducing average and maximum absolute output errors of 0.430% and 0.927%, respectively, of the maximum absolute output value under transient fault injection
Optimum wordlength allocation
Published versio
Heuristic datapath allocation for multiple wordlength systems
Published versio
FPGA Architecture Optimization Using Geometric Programming
Volume 4 No 13 of the periodical Progression. Published November, February, May and August by The Radiant Healing Centre. SPCL PER BT 732 P76 V.1,1932-V.5,193
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits
Published versio
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